1. Field of the Invention
The disclosed subject matter relates generally to the fabrication of semiconductor devices and, more particularly, to forming a folded ballistic conductor interconnect line.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of circuit functions. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines and the spaces between the metal lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit area.
Interconnect lines can be generally categorized into three groups: signal, clock and power lines. These interconnect types have different and, in some cases, opposing requirements. Signal lines require small capacitance and are less sensitive to resistance especially for short interconnects. Signal lines are almost immune from electromigration because they pass bidirectional currents. Thus, for signal lines, low aspect ratio lines are favored. Clock lines, which have an activity factor of 1, require low resistance and small capacitance. Clock lines, however, can fail due to electromigration because of the large currents they pass and because, in some cases, the current path is different in charge and discharge durations. Power lines are particularly susceptible to electromigration failure due to large currents flowing mainly in one direction.
In integrated circuits, one limiting factor as it related to device performance is the signal propagation delay caused by the switching speed of the transistor elements. However, as the channel length of these transistor elements has now reached 50 nm and less on more modern integrated circuits, the signal propagation delay is no longer limited by the switching speed of the field effect transistors. Rather, the signal propagation delay is limited in large part, owing to the increased circuit density, by the interconnect lines, since the line-to-line capacitance (C) is increased and also the resistance (R) of the lines is increased due to their reduced cross-sectional area. The parasitic RC time constants for signal lines tends to limit the performance of the semiconductor devices.
Conventional dual damascene interconnect techniques typically result in lines having the same aspect ratio in a particular metallization layer. Hence, it is difficult to optimize the constructs of the lines depending on their intended function: signal, clock or power.
The present application is directed to various methods for forming folded ballistic conductor interconnect lines so as to eliminate or reduce the effects of one or more of the problems identified above.